This invention pertains to a differential transimpedance amplifier. More particularly, it pertains to a high frequency low impedance differential transimpedance amplifier.
Transimpedance amplifiers convert a current level to a voltage level and are effective in various types of circuits providing easier circuit integration, more precise control and increased accuracy in performance. A typical use of a transimpedance amplifier is to sum currents as part of a frequency impulse response filter.
An ideal transimpedance amplifier has zero input impedance and infinite output impedance. This ensures that the entire current flows only across a load, or output resistor, to convert the current to a voltage level. By approaching zero input impedance and infinite output impedance, the performance of a transimpedance amplifier is improved.
Use of a transistor to function as the transimpedance amplifier to sum a number of currents is known in the art. The currents to be summed are generally connected together at the emitter of the transistor so that the total current flows across the load or output resistor connected to the collector of the transistor when the base of the transistor is properly biased. The load or output resistor is sized appropriately to effectively diminish any effect the output impedance of the transistor would have on the load or output resistor.
Use of a transistor in this configuration for summing a number of currents creates an input impedance equal to at least the base spreading resistance (r.sub.b) divided by the transistors current gain and the incremental resistance of the emitter-base (r.sub.e) for its bias condition. The resistance r.sub.e is usually much larger than r.sub.b /Beta and therefore the input impedance is approximately equal to the resistance r.sub.e of the transistor. However, although small, the resistance r.sub.e will interact with parasitic capacitance which exists at the emitter of the summing transistor as a result of connecting together the current supplies to be summed as well as the capacitance that exists in the line. This interaction generates a voltage excursion or voltage level at the emitter node of the transistor as the parasitic capacitance charges or discharges in response to the interaction. The time constant associated with the parasitic capacitance charging and discharging creates a time delay to the circuit as not all of the current to be summed flows across the load or the output resistance located at the collector. This time constant decreases the frequency rate at which the circuit can accurately operate and thus decreases the bandwidth of the circuit.
To avoid this decrease in bandwidth and improve the accuracy of a transimpedance amplifier, the input impedance must be minimized to approximate ideal conditions (i.e. zero input impedance).